1. Field of the Invention
The present invention relates to packet processing; and, more particularly, to a system and method for buffering packets.
2. Related Art
There is great interest today in the question of how to reduce power consumption in electronic equipment. One power saving mechanism in printers is to shut down power to a system-on-a-chip (SoC) including the CPU for the engine and controller. The power saving mode requires support, so power is supplied only to the communication controller.
When a print-out request is received via the network during power saving mode, the printer returns to normal operating mode. After returning to this mode, packets coming in from the network are processed. The power-up sequence and booting in the return from the power saving mode to the normal operating mode require at least several hundred milliseconds (ms). During this time, the packets coming in from the network are dropped.
In order to reduce the number of packets dropped during this time, a buffer is provided in the communication controller receiving a supply of power during the power saving mode. However, a buffer in the communication controller consumes power, and it is critically important to minimize power consumption during the power saving mode which the printer resides in most of the time. When a large buffer is provided in the communication controller to reduce the dropping of packets, the increase in power consumption is proportional to the size of the buffer. When it takes more time to return to the normal operating mode, the size of the buffer and the amount of power consumed increases accordingly.
FIG. 1 shows an example of an energy efficient SoC with a packet buffer incorporated into the communication control unit. The SoC 100 has a voltage island (VI) area 110 in the communication controller which is powered at all times to monitor the network, a main area 120 to which power is shut down during standby mode, and a fence gate 130 separating these areas. The VI area 110 includes power management 111, packet filter management 112, a packet filter 113, and a buffer 114. The main area 120 includes reset logic 121, a CPU 122, an Ethernet media access controller (MAC) 123, and memory 124.
The power management 111, packet filter management 112, packet filter 113 and buffer 114 are configured using Wake-on-LAN (WOL) LSI circuits. These are embodied for example using a startup logic circuit, Ethernet packet analyzer/responder circuit, and a packet buffer circuit. The power management 111 receives the input of each power-good and reset signal to manage power supplied to the packet filter management 112 and the reset logic 121. The packet filter management 112 manages the packet filter 113 and the buffer 114, the packet filter 113 filters packets from the Ethernet receiver and outputs them to the buffer 114, and the buffer 114 holds the packets during the power saving mode and outputs them to the Ethernet MAC 123 during the normal operating mode. The Ethernet MAC 123 outputs the packets inputted from the buffer 114 to the CPU 122 and the memory 124. The reset logic 121 outputs reset signals to the CPU 122 and the Ethernet MAC 123, or to a phase-locked loop (PLL) and a built-in self-test (BIST) as well.
In a SoC 100 of the prior art, large-sized memory is provided as the buffer 114. Because this increases the circuit size of the VI area 110 itself, which receives power at all times, the amount of power consumed during power saving mode increases. Because the buffer 114 in the VI area 110 is separate from the memory, more power is consumed during the power saving mode, and the high-speed memory of the main area 120 cannot be obtained in the VI area 110 beyond the fence gate 130. Network retransmission is expected and dropped packets are tolerated, but this does not reliably contribute to the prevention of dropped packets because there is a limit to the number of retransmissions. A pause packet can be sent to temporarily stop frame transmission, but some hubs cannot use pause packets. Thus, the prior art does not provide a foolproof solution.
A network device is disclosed in Japanese Laid-open Patent Publication No. 2005-302002 which switches between two buffers, one for sleep mode and another for normal mode, so that packets are not dropped. A packet processing device is disclosed in Japanese Laid-open Patent Publication No. 2009-224867 which can save power when the input packet interval has been increased and the input traffic volume has been decreased. A printing device is disclosed in Japanese Laid-open Patent Publication No. 2003-191570 in which the CPU executes power saving controls when a packet has not been received within a predetermined period of time.